LPRF microcontrollers are frequently used in low duty-cycle applications, an example of which is a battery powered light sensor. In such applications the light sensor may be controlled to take a measurement periodically and transmit the data based on that reading. Such an operation may take less than 10 ms. In such an application the electric current used will be dominated by the sleep or standby current. Therefore reduction of the sleep current in such microcontrollers may prove valuable for improving battery lifetimes.
When a microcontroller goes to sleep it may typically disable all circuitry except a sleep timer consisting of a low power sleep oscillator and a counter which is preloaded with a value corresponding to the sleep period. For example if the sleep oscillator is running at a frequency 32 Khz and a sleep period of one minute is required then the counter value would need to be 32000*60=1,920,000. The system would load the counter with this value, enable the oscillator circuit and then go to sleep by disabling all other circuitry to save power. For each oscillator period the counter will decrement until it reaches zero at which point an interrupt will be triggered which wakes the microcontroller up. During the sleep period the current consumption may be dominated by the sleep oscillator circuit.
An example of a known sleep oscillator is shown in FIG. 1 with corresponding voltage and current waveforms VA, VB, VC, VD, VE, IC, ID shown in FIG. 2. For brevity the main RC relaxation oscillator is not shown, however this is arranged to generate a signal VA which is a triangular signal of a few hundred mV. This signal is passed to a comparator circuit of the sleep oscillator which feeds into a series of Inverters 1, 2 to generate the final output clock signal. This clock signal is then used to drive sleep timers and associated logic in the microcontroller. It will be appreciated by the skilled person that the Inverters 1, 2 shown in FIG. 1 are implemented as cmos inverters, however, alternative implementations are also possible.
Waveform ID in FIG. 2 shows the current through Inverter 1, it can be seen that the current is zero for most of the cycle but as the input signal changes it rises up to a maximum value before dropping down to zero again. This effect is termed “shoot through current” and is caused when the input signal to Inverter 1 reaches a value where both the nmos and pmos devices are simultaneously turned on and conducting current. Note that there is a parasitic capacitance at the node VD, mostly due to the gate capacitance of the transistors in Inverter 2, which causes VD to rise/fall at a finite rate depending on the amount of current that can be supplied by Inverter 1. As shown in FIG. 2 VD has a shorter rise/fall time than VC and the shoot through current IE of Inverter 2 is present for a shorter time than that of inverter 1 and reaches a lower maximum value.
The final output signal VE must be of full amplitude with a high voltage close to Vdd and a low voltage close to a ground GND (or Vss) so that it can be used to drive logic gates, similarly the signal edges must have a fast rise and fall time and a strong drive strength so that the preceding logic gates switch quickly with minimum shoot through current. Note that there will also be a parasitic capacitance at node VE due to any subsequent logic gates, we could therefore improve the output edge speed at VE by increasing the width of the devices in Inverter 2 so that they could drive more current and charge/discharge this capacitance quicker, however making these devices larger would increase the parasitic capacitance at the input of Inverter 2 meaning that the rise/fall time of VD would then be reduced leading to a larger shoot through current in Inverter 2.
A chain of inverter stages can be used to sharpen up the edges of a signal so that the rise/fall time of the final stage is much less than the first stage. Each inverter stage has associated shoot through current which is undesirable. We can achieve the same output edge speed by using a chain of fewer inverters with increased width transistors, but due to the increased parasitic capacitance on the input of each stage we may find that the average current remains the same or even increases. It is necessary to generate the signal VE from VB using as little current as possible and in general we find that whilst this can be achieved using a chain of inverters there is a limitation on the minimum amount of current required. In addition this current is poorly defined and may change significantly with voltage, temperature and process variation.